The  transition to 58G and 112G transceivers is a step towards 400G and 800G+ data rates on the same existing footprint.

Xilinx is demonstrating full-duplex 112G PAM4 signaling on a single lane.  112Gb/s transceiver performance is necessary to address next-generation optical networking and line card densities.  Programmable devices with 112G transceivers will be in Xilinx’s upcoming 7nm portfolio.

Built on the Virtex UltraScale+ class of devices for high-end applications, the transceiver architecture enables customers to effectively double the bandwidth capabilities of existing systems by combining the flexibility of programmable logic with 58G PAM4 transceivers.

These devices can operate over existing 25G backplanes, extending the life and bandwidth of current systems while paving the way for the next generation. For migration, the new devices with 58G transceivers are footprint compatible with existing Virtex UltraScale+ devices in production today.

Targeted at cloud computing, 5G networking, core networks (OTN, Ethernet) and network functions virtualization (NFV) applications, this latest transceiver architecture will enable vendors to scale 50G, 100G and 400G ports and terabit interfaces in compact and less complex system designs.

“Networks are changing dramatically to enable faster, more flexible and more adaptable systems, and the industry is gearing up in anticipation of the change with new optics and standards,” says Xilinx’s Farhad Shafai, “we are proud to be leading the way in delivering the most flexible and adaptable solutions to our customers, along with production-proven silicon, a track record of quality and in tandem with the ecosystem of optics, backplanes and other key technologies in development.”

The new 58G PAM4 Virtex UltraScale+ devices include integrated PAM4 transceivers, 100GE IP blocks, and all associated FEC required for next-generation interconnect.