Andes adopts UltraSoC


“We are collaborating with mutual customers on implementations which utilise the  V5 AndeStar architecture with the support of UltraSoC’s SoC analytics and debug IP, and processor trace, ” says UltraSoC CEO Rupert Baines (pictured).

Andes will leverage UltraSoC IP to accelerate development and enhance debugging of embedded products.

UltraSoC offers a commercial RISC-V development environment, with SoC analytics, processor trace and other options.

UltraSoC developed processor trace for RISC-V in 2017, and shortly afterwards offered its trace specification for use by the RISC-V Foundation as part of its standardization effort.

The company remains committed to supporting the RISC-V Foundation standard run-control/debug and the proposed processor trace format, in line with its wider strategy of providing integrated debug and development solutions for any processor architecture.

Andes’ cores are based on the AndeStarTM V5 32-bit and 64-bit architectures. The partnership with UltraSoC allows customers for Andes V5 N25 and NX25 processors to have advanced embedded analytics capabilities integrated as an option.

Customers using Andes’ high-performance 32 and 64-bit processor cores gain access to UltraSoC’s SoC analytics and debug IP in addition to RISC-V processor trace, which together give designers full visibility not only of the performance of the core but into the operation of the entire system.

Andes has adopted RISC-V for its fifth generation processor architecture, the AndeStar V5, and launched two high-end processor cores in its AndesCoreTM family of configurable processor IP: the 32-bit N25 and the 64-bit NX25.

Both are RISC-V based and deliver in excess of 3.4 CoreMark/MHz, with gate counts as small as 30K (N25) and 50K (NX25), and a maximum clock rate of 1.1 GHz when using TSMC’s 28nm HPC process. The N25 and NX25 are suitable for high-speed control tasks.





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