DAC: Planning tools are based around unified hierarchical database

Avatar at DAC 2018

by Caroline Heyes

The tools are built on ATopTech technologies which were the subject of a lawsuit brought by Synopsys. Following that, the tools were rebuilt, the command which had been the same as the Synopsys command was changed, explained Lily Cheng, manager of applications engineering, Avatar.

Aprisa has placement, clock tree synthesis, routing, optimisation and embedded analysis engines for IC design. It supports standard data inputs and outputs, including Verilog, SDc, LEF/DEF, Liberty and GDSII. The patented technologies were developed specifically to deal with the design challenges at 28nm and below with its place and route tools certified by semiconductor foundries for designs at 28nm, 20nm, 16nm, 14nm, 10nm and 7nm process nodes.

The placement tool dynamically and automatically selects dominant scenarios for optimisation to efficiently include all sign-off scenarios during physical implementation to reduce the number of design iterations.

It also supports all EM rules of advanced process nodes with integrated EM checking and fixing during routing.
Internal analysis engines correlate with the foundry-approved sign-off tools for predictable design closure, explained Cheng.

Another feature is near sign-off timing analysis. The embedded timer correlates with sign-off timing tools and supports various on-chip variation methods, including AOCV, SBOCV, SOCV and LVF. It also supports graph based and path based analysis and optimisation and advanced signal integrity and noise analysis. All timing features are enabled during optimisation, which is claimed to increase the speed of convergence.

Color-Aware DPT routing is the company’s patented routing technology which uses correct-by-construction methods to avoid double-patterning technology violations during DRC sign off.

Both UPF and CPF are supported for low power-driven optimisation, with leakage and dynamic power driven optimisation.

Apogee shares the Aprisa’s analysis engine and database for correlation between bock and top level timing. It provides a seamless, integrated design environment for complex chip designs with low power consumption and die size. The multi-threaded and distributed system is designed for high computational throughput.

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