Caled RAMLinx, it enables customization of an eFPGA array to exactly fit customers’ needs.
A patent for this approach has been granted to FlexLogix co-founders Geoff Tate and Cheng Wang.
“Traditional FPGA technology used by our competition is not capable of achieving the flexibility and advantages that this patent describes,” says Tate, “this is a major competitive advantage for our customers because their applications require many different types of RAM in various amounts. Traditional FPGA technology offers only “block RAM,” or dual port RAM, typically in a fixed ratio of RAM to LUTs. With the Flex Logix architecture, customers can have no RAM, a little RAM or a lot of RAM and they can specify single-port RAM, dual-port RAM, and the type of RAM including specialty RAM such as TCAM.” In addition, the RAM can optionally have parity or ECC as needed.
The technology builds on the tiling architecture of the EFLX eFPGA to utilize the otherwise unused input and output pins of each tile not on the perimeter of the array to provide flexible connections to any kind of RAM located between the tiles of the eFPGA array.
The ArrayLinx mesh connection is routed over top of the RAMs to provide connectivity between tiles of the EFLX eFPGA. The integrated RAM is an integral part of the eFPGA array and is programmed by the EFLX compiler. A RAMDEF file informs the EFLX compiler of the characteristics of the integrated RAM. Typically, the integrated RAM is based on TSMC Memory Compilers, but could also be custom RAM the customer supplies such as TCAM.
The idea of integrating RAM between tiles can also be extended to integrating any kind of custom logic block between tiles – again enabling customization of an eFPGA array to exactly fit the customer’s needs. As with the RAM, the custom logic block, e.g., a digital signal processor, is connected to the logic tiles via the otherwise unused input and output pins of one or more of the adjacent tiles.