Esperanto Technologies will present at the RISC-V Workshop in Barcelona next week, (May 7-10) potential changes to high-performance RISC-V processors intended to eliminate speculation-based timing attacks, such as Spectre and Meltdown.
The California-based developer of RISC-V processors is proposing the use of RISC-V cores which minimise changes to the RISC-V ISA or platform specifications in order to provide security against timing-based attacks.
These proposals are being previewed with the RISC-V community to solicit comments prior to implementation in RISC-V chips.
Esperanto president and CEO Dave Ditzel, writes:
“Our goal is to make RISC-V the architecture of choice for the most demanding AI and machine learning applications, driving computing innovation for the next decade.”
To this end Esperanto is active in the RISC-V ecosystem and in several mission-critical technical working groups and committees.
Esperanto will describe a 64-bit free and open RISC-V supercomputer-on-a-chip for artificial intelligence (AI) designed with leading edge 7nm CMOS.
Rick O’Connor, executive director of the non-profit RISC-V Foundation, writes:
“Esperanto exemplifies how members of the RISC-V community are working together to accelerate the wide adoption of the RISC-V architecture, and for expanding our partner and developer ecosystem.”
Also in Barcelona, Espasa will present a summary of the latest updates to the Vector ISA specification for the RISC-V architecture.
The Barcelona RISC-V conference is co-hosted by the Barcelona Supercomputing Center (BSC) and the Universitat Politècnica de Catalunya (UPC) and sponsored by NXP and Western Digital.
The RISC-V Workshop Barcelona 2018 will feature an Esperanto exhibit and several presentations by Esperanto.
Esperanto Technologies also has engineering sites in the EU and Eastern Europe.