The newly developed circuit operates with 55% of the power requirements of previous technology for optical modules in Ethernet used for communication between servers and switches in datacenters.
With the spread of big data analysis and cloud services, there has been a demand for faster and denser optical modules in order to provide high data transfer capability between servers and switches, which has necessitated miniaturization and reductions in power consumption.
To speed up and miniaturize optical modules, referenceless CDR technology has been developed that does not require a crystal oscillator to produce the standard timing. With existing referenceless CDRs, however, the circuit that detects discrepancies in the timing cycle for reading input data has high power consumption, leading to problematic heat generation and causing difficulties in increasing circuit density.
Previously, in order to detect discrepancies in the data-reading cycle, it was necessary to detect the signal four times with different timing for each bit of data, with the power consumption for each timing generator taking up a significant proportion of the power consumption of the module as a whole.
Now, the University of Toronto and Fujitsu Laboratories have developed a new timing extraction technology that can operate on the same cycle as the data transmission speed, detecting once for each bit discrepancies in the reading cycle from amplitude information in the input signal. The result is that the number of timing generators can be reduced to one-fourth that of previous architectures, successfully cutting power consumed by the optical module as a whole to about 70% that of previous technologies.
This technology lowers the power consumption of optical modules, enabling high traffic transmission capability through denser implementations and thereby improving datacenter processing capability.
Reducing the number of components in optical modules is an effective way to reduce the power consumption and improve miniaturization. For this reason, referenceless CDRs, which do not require a standard timing (reference), are used to enable the elimination of the crystal oscillator.
The circuits that regulate the observation of the input signal and the reading of data in existing referenceless CDRs, however, must operate at high speed, leading to high power consumption, as well as difficulties in high density installation due to heat that accompanies this power consumption.
With existing referenceless CDR architectures, the CDR decides whether each bit of data is a 1 or a 0 four times, and the data-reading cycle is regulated by observing changes in the results of each decision.
The input signal is observed with respect to clocks 1 through 4-generated by the timing generators- as it changes from 0 to 1, and each bit is assigned a 1 or a 0. This makes it possible to observe between which two clocks the data changed from 0 to 1 or vice versa. For example, as shown in Fig. 2, when the crossover point is observed to change from A-B-C-D, it can be understood that the data-reading cycle is shorter than the input signal. If the opposite change, from D-C-B-A, is observed, it can be understood that the data-reading cycle is longer than the input signal.
With this technology, the power consumption of referenceless CDRs can be reduced to 55% that of previous architectures, cutting power consumption of optical modules to 70%. This means it is now possible to implement optical modules in higher densities than before. This is expected to contribute greatly to improving the performance of datacenters.