UltraSoC and NetSpeed to accelerate SoC design time


Rupert-Baines

UltraSoC’s IP enables designers to create an on-chip infrastructure that non-intrusively monitors a chip’s behavior, both hardware and software. It is designed to give engineering teams a view “inside” SoCs and help get designs working quickly and reliably.

This IP provides designers with an understanding of the interactions between on-chip processor blocks, custom logic, and system software. The IP enables analytics, forensics, and optimisation features that provide continual analysis, even after the product has been shipped to the end customer.

“Today’s SoCs, particularly those used in the most demanding applications including automotive, hyperscale computing, and mixed reality, rely on a flawless and efficient interconnect such as NetSpeed’s coherent on-chip network IP,” says UltraSoC CEO Rupert Baines (pictured), “the integration of UltraSoC’s monitoring and analytics capability with NetSpeed’s interconnect gives chip architects and designers an unprecedented ability to quickly understand how ultra-complex SoCs behave. This can have a dramatic effect on development schedules and budgets by reducing engineering time and effort, and getting high quality products out much faster.”

A  Netspeed and UltraSoC webinar entitled: Debug, Analytics, NoC, and beyond… Exploring uncharted galaxies of interconnects! Will take place on November 2, at 17:00 GMT (UK time). To see more details of the webinar and to register for the event use this link.



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