The IoT reference platform has been taped out using TSMC’s commercially available 40nm Ultra Low Power (40ULP) process technology.
TSMC’s 40nm process integrates 193nm immersion lithography technology and ultra-low-k connection material to increase chip performance, while simultaneously lowering power consumption.
Specifically developed for IoT and wearable applications, TSMC’s 40ULP process cuts leakage current by up to 70% and lowers power consumption by up to 30% compared to its Low Power (LP) process.
The platform incorporates derivations of sureCore’s EverOn and PowerMiser SRAM IP product lines.
sureCore’s SRAM IP is capable of operation at near-threshold bit cell retention voltages and delivering significant dynamic/static power savings.
EverOn is capable of operation with supply voltages between 1.21V and 0.6V on commercially available 40ULP processes, across process corners, and across a -40°C to +125°C temperature range.
The PowerMiser SRAM family delivers more than 50% dynamic power savings and approximately 20% static power savings compared to industry standard SRAMs available on commercially available 40ULP processes.
“With its understanding how near threshold design can meet customer expectations for battery powered applications, we knew that EnSilica would be able to proceed quickly to successful tape-out,” says sureCore COO Eric Gunn, “EnSilica’s technical appreciation of our technology, as well as deep understanding of TSMC’s processes, has ensured a painless route to tape-out.”
“sureCore’s EverOn and PowerMiser SRAM IPs are proving a game-changer when it comes to providing SoC developers with ultra-low power, area-efficient memories,” says EnSilica CEO Ian Lankshear.