Built on a 28nm SONOS flash CMOS process licensed from Cypress, the devices, called PolarFire, have 12.7Gbps transceivers, hardened I/O gearing logic for DDR memory and low-voltage differential signaling (LVDS), security IP and clock and data recovery (CDR) capable 1.6 Gbps I/Os.
“The transceivers use half of the power of competitors’ transceivers,” Microsemi’s Ted Marena (pictured) told EW.
Microsemi reckons the new family increases its FPGA addressable market to over $2.5 billion particularly within the communications infrastructure market by reducing opex, capex and thermal/carbon footprints.
“We’ve had an early access programme running for eight months, “ said Marena, “the software is with over a hundred customers.”
The family addresses the reliability concerns that face SRAM-based FPGAs as they relate to single event upsets (SEUs) in their configuration memory.
“They are immune to single event upsets,” said Marena, “SRAM customers have to work around that.”
Debug time is reduced by its SmartDebug feature.
“Our customers tell us that a third of the time spent in programming is spent on debug,” said Marena, “with PolarFire SmartDebug you can pick any two points inside the device and you can view them on an oscilloscope. It’s like having an oscilloscope on the chip. No recompiling is required.”
In collaboration with Silicon Creations, Microsemi has developed a 12.7 Gbps transceiver optimized to be area efficient and low power, resulting in total power of less than 90mWs at 10 Gbps.
“For the first time a non-volatile FPGA provides tangible power and cost benefits over SRAM FPGAs that feature 10 Gbps transceivers,” claims Microsemi’s Bruce Weyer.
The chips have static power of 25 mW at 100K logic elements (LEs), zero inrush current and FlashFreeze mode for standby power of 130 mWs at 25 degrees C.
Microsemi provides customers with a power estimator to analyse power consumption of their designs. After implementation, the SmartPower Analyzer can be used to access full design power.
There is built-in single error correction and double error detection (SECDED) as well as memory interleaving on LSRAMs, and system controller suspend mode for safety critical designs.
PolarFire FPGAs offer Cryptography Research Incorporated (CRI) patented differential power analysis (DPA) bitstream protection, integrated physically unclonable function (PUF), 56 KB of secure embedded non-volatile memory (eNVM), built-in tamper detectors and countermeasures, true random number generators, integrated Athena TeraFire EXP5200B Crypto Co-processors (Suite B capable) and a CRI DPA countermeasures pass-through license.
“PolarFire FPGAs enable customers to forego purchasing FPGAs with higher power and cost to obtain the 12.7G transceiver performance required for many mid bandwidth applications,” says Microsemi’s Shakeel Peera, “combining PolarFire FPGAs with Microsemi ASSPs enables end-to-end solutions in timing, voice processing, storage, Optical Transport Network (OTN) switching and transport, and power management across multiple market segments.”